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Sreeja Rajendran

Sreeja Rajendran
Sreeja Rajendran
 
PhD (Electrical and Electronics Engineering), Birla Institute of Technology and Science, Pilani, Dubai Campus

Contact Details

 
079-68261707
 
#3108, FB-3, DA-IICT, Gandhinagar, Gujarat, India – 382007

Biography

Dr. Sreeja Rajendran completed her PhD in Microelectronics (Hardware Security) from Birla Institute of Technology and Science, Pilani. She joined DA-IICT in October 2021. Prior to joining DA-IICT she has taught in engineering colleges in India, Bahrain and Oman. Her areas of research interest include Har dware Security,  MEMS, Quantum Dot Cellular Automata, Test based and Fault Tolerant Circuit Architecture Design. She teaches courses on Digital Logic Design, Computer Organization and VLSI Test. She has authored papers in various international journals and presented works at IEEE and Springer conferences.

Specialization

VLSI, Embedded Systems and MEMS, Hardware Security, VLSI Test

Publications

Journal Articles:

  • S. Rajendran and M.L. Regeena, “A Novel Algorithm for Hardware Trojan Detection through Reverse Engineering”, IEEE Transactions Computer Aided Design (accepted on April 2, 2021). doi.org/10.1109/TCAD.2021.3073855 (Impact factor 2.168, Indexed in SCI, SCOPUS and WoS)
  • S. Rajendran and M.L. Regeena, “Sensitivity Analysis of Testability Metrics for Secure IC Design”, IET Computer and Digital Techniques, vol. 14, no. 4, pp. 157-165, April 2020. doi.org/10.1049/iet-cdt.2019.0217 (Impact factor 0.803, Indexed in SCIE, SCOPUS and WoS)
  • S. Rajendran and M.L. Regeena, “Application of Testability Analysis in Hardware Security”, International Journal of Advanced Science and Technology, vol 29, no.5, pp. 7777-7791, May 2020. (SCOPUS indexed)
  • S. Rajendran and M.L. Regeena, “An Efficient Software Tool based on SCOAP for Testability Analysis of Combinational Circuits”, International Journal of Simulation -- Systems, Science & Technology, vol. 20, no.1, p1-10, Feb 2019.

Book Chapters:

  • S. Rajendran and M.L. Regeena, “Security Threats of Embedded Systems in IoT Environment”,Inventive Communication and Computational Technologies, in Lecture notes in Networks and Systems, Springer Publications, Jan 2020, pp.745-754. doi 10.1007/978-981-15-0146-3_70
  • S. Rajendran and M.L. Regeena, “Security of an IoT Network: A VLSI point of view”, Inventive Communication and Computational Technologies, in Lecture notes in Networks and Systems, Springer Publications, Jan 2020, pp 789-798. doi 10.1007/978-981-15-0146-3_75
  • S. Rajendran and M.L. Regeena, “FinFET Optimization in the design of 6T SRAM cell”, Modelling simulation and Intelligent Computing, Chapter 65, Lecture Notes in Electrical Engineering, Springer Publications, July 2020, pp 598-607. doi 10.1007/978-981-15-4775-1_65

Conference Papers:

  • S. Rajendran and M.L. Regeena, “Fin FETs and their Application as Load Switches in Micromechatronics”, in IEEE International Symposium on Nanoelectronic and Information Systems (INIS), Indore, India, pp. 152-157, 2015.
  • S. Rajendran and M.L. Regeena, “Ab-initio study on FinFETs and their application in loT aided robotics”, in Sixth International Symposium on Embedded Computing and System Design (ISED),Patna, India, pp. 38-42, 2016.
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