Journals

• G. Bhatti, T. Pathade, Y. Agrawal, V. Palaparthy, B. Gohel, R. Parekh, and M. G. Kumar, “Neural network-based fast and intelligent signal integrity assessment model for emerging MWCNT bundle on-chip interconnects in integrated circuit,” Taylor and Franscis, IETE Journal of Research, pp. 1-16, 2023.
• T. Pathade, Y. Agrawal, R. Parekh and M. G. Kumar, "Structure fortification of mixed CNT bundle interconnects for nano integrated circuits using constraint-based particle swarm optimization," IEEE Transactions on Nanotechnology, vol. 20, pp. 194-204, 2021.

Conference

• T. Pathade, Y. Agrawal, R. Parekh, and M. G. Kumar, “Efficient low power ALU design with incorporation of MWCNTB on-chip interconnects, ” in Proc. IEEE 24th Electronics Packaging Technology Conference (EPTC), 2023- Received Travel grant award for paper presentation.
• T. Pathade, Y. Agrawal, R. Parekh, and V. Palaparthy “Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects,” in Proc. Materials Today Proceedings, vol.43, no.6, pp. 3874-3879, 2021.
• T. Pathade, Y. Agrawal, R. Parekh, and M. G. Kumar, “CNTFET based low power repeaters for on-chip interconnect system,” in Proc. International Symposium on VLSI Design and Test, vol. 25, 2021.
• T. Pathade, U. Shah, Y. Agrawal, and R. Parekh, “Preeminent buffer insertion technique for long advanced on-chip graphene interconnects,” in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 1-3, 2018.

Book Chapter

• T. Pathade, Y. Agrawal, R. Parekh, and M. G. Kumar, “Prospective incorporation of booster in carbon interconnects for high speed integrated circuits,” Springer Book Chapter, International Conference on Advances in VLSI and Embedded Systems (AVES-2019), pp. 273-288, 2020.