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Faculty

Rutu Parekh

Rutu Parekh
PhD (Electrical Engineering), Sherbrooke University, Canada
079-68261553 # 2112, FB-2, DA-IICT, Gandhinagar, Gujarat, India – 382007 rutu_parekh[at]dau[dot]ac[dot]in https://sites.google.com/view/rutumparekh/home?authuser=1

Dr. Rutu Parekh is an Associate Professor at School of Technology, DAU, Gandhinagar, India, with over a decade of experience in VLSI design, nanoelectronics, embedded systems, and IoT applications. She completed her M.Tech in Electrical Engineering from Concordia University, Canada, her Ph.D. in Electrical Engineering from Université de Sherbrooke, Canada, and was a Postdoctoral Fellow at the Centre of Excellence in Nanoelectronics, IIT Bombay.

Her research focuses on high-voltage ASIC design for space applications, long-distance wireless sensor networks, and IoT-enabled smart agriculture and environmental monitoring systems, including soil moisture and irrigation prediction, forestation tracking, and real-time GUI-based monitoring. She has led sponsored projects on long-distance military communication systems and developed innovative prototypes integrating advanced sensors and secure data transmission.

She has industrial experience with eInfochips, Ahmedabad and HP Karkland, Montreal, Canada, research experience with Ecole Polytechnic, Quebec, Canada, and teaching experience with Nirma University of Science and Technology, Ahmedabad. Presently, she is also associated with The Inter-University Centre for Astronomy and Astrophysics, Pune, India, as a Visiting Associate. She has authored book, published numerous international papers, filed patents, and contributes as semiconductor board member, editorial board and technical committee member. She actively mentors Ph.D. and postgraduate students and supports semiconductor workforce development in India.

High-Voltage ASIC Design for Space Applications, Nanoelectronics and Emerging Devices, Embedded Systems and IoT Applications, Long-Distance Wireless Communication Systems, Smart Agriculture and Environmental Monitoring, Memristor-based Neuromorphic Circuits

  • DNA Based Hybrid Circuit Design Approaches, Patel, R. and Parekh, R., IEEE 5th International Conference for Convergence in Technology (I2CT), India, Mar. 29-31, 2019
  • Novel Subthreshold Modeling of Advanced On-chip Graphene Interconnect using Numerical Method Analysis, Patel, N., Agrawal, Y. and Parekh, R., IETE Journal of Research, Taylor and Francis, Oct, 2018.
  • A Vector File Generation Program for Simulating Single Electron Transistor Based Computing System, Patel, R., Agarwal, Y., Parekh R., IEEE Electron Device Kolkata Conference (IEEE EDKCON), India, 2018.
  • Contemporary On-chip System Modeling using FDTD in Low Power Regime, Agrawal, Y., Chandel, R., Girish, M., Parekh, R., IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2018, India, December, 2018.
  • Preeminent Buffer Insertion Technique For Long Advanced On-Chip Graphene Interconnects, Pathade, T.,Shah, U., Agrawal, Y., Parekh, R., IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2018, India, December, 2018.
  • Prospective current mode logic for on chip interconnects in integrated circuit design, Agrawal, Y., Chandal, R., Kumar, G., Parekh, R., in book titled: IET VLSI and Post-CMOS Devices, Circuits and Modelling, 2018.
  • Design and Implementation of Autonomous UAV Tracking System Using GPS and GPRS, Thakkar, D., Rajput, P., Dubey, R., and Parekh, R., 2nd ICACIE, 2017 – Best Springer paper award in Intelligent Networking Track.
  • Modeling and simulation of 1/f noise during threshold switching for Phase Change Memory, Parekh, R., Shojaei, M., and Rajendran, B., Lecture Notes in Electrical Engineering (LNEE), Springer, ICACCP, 2017.
  • Noise removing filters and its implementation on FPGA, Mishra, A. and Parekh, R., Lecture Notes in Electrical Engineering (LNEE), Springer, ICACCP, 2017.
  • Gargave, Y. Agrawal, R. Parekh, “Single Precision Floating Point Matrix Multiplier using Low Power Arithmetic Circuits”, Lecture Notes in Electrical Engineering (LNEE), 1st Springer International Conference on Emerging Trends and Advances in Electrical Engineering and Renewable Energy (ETAEERE-2016), India, 17 – 18 Dec, 2016. DOI: 10.1007/978-981-10-4394-9_67
  • Parekh, J. Beauvais, and D. Drouin, “SET logic driving capability and its enhancement in 3-D integrated SET-CMOS circuit”, Microelectronics Journal, 45, pp. 1087-1092, 2014. DOI: 10.1016/j.mejo.2014.05.020, Citations : 5.
  • Parekh, A. Beaumont, J. Beauvais, and D. Drouin, “Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room Temperature Operation”, IEEE Transactions on Electron Devices, Vol. 59, No. 4, pp. 918-923, 2012.DOI: 10.1109/TED.2012.2183374, Citations : 16

Selected Publications & Patents (Short Version)

  • Parekh, R., & Dhavse, R. (2023). Nanoelectronics: Physics, Technology and Applications.
  • Patent: High Voltage Integrated Bias Driver ASIC for Driving Imaging Photo Sensor Devices.
  • Numerous journal and conference articles on high-voltage ASICs, embedded systems, IoT, and nanoelectronics.

Google Scholar Profile: https://scholar.google.com/citations?user=B3RkZQkAAAAJ

  • Nanoelectronics
  • ASIC Design
  • Analog Circuits / Analog Electronics
  • VLSI Subsystem Design
  • CMOS Digital Design
  • Selected Topics in VLSI
  • Introduction to VLSI
  • Computer Organization and Programming
  • Basic Electronics
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