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Yash Agrawal

Yash Agrawal
Yash Agrawal
 
PhD (Electronics & Communication), NIT Hamirpur

Contact Details

 
079-68261629, 9882114669
 
# 1101, FB-1, DA-IICT, Gandhinagar, Gujarat, India – 382007
 
http://www.linkedin.com/in/yash-agrawal-525b021a/

Biography

Dr. Yash Agrawal received his Ph.D. and M.Tech. Degrees in VLSI Design Automation and Techniques in E&CE Department from National Institute of Technology, Hamirpur, Himachal Pradesh, India.

Dr. Yash has been expert and distinguished guest at various places. He is Editor and Reviewer of several reputed Journals. He has been Secretary and Coordiantor of various forums and events. He has organized several workshops and part of the organizing committee in various Trainings, Seminars, and Conferences. He has been the Chairman and awarded with best forum member of IETE Forum at KITS Ramtek, Nagpur Division during 2008-2009.

He has been awarded with prestigious IETE—K S Krishnan Memorial Award-2017 for the Best System Oriented research paper. He achieved third place in All India Mentor Graphics design contest held at Bangalore, India in 2011. He has received 2nd Runner up and Cash Prize of Rs. 50,000/- in All India Mentor Graphics Design Contest held at Bangalore.

He has several publications in Book Chapters of Springer, Journals including IEEE Transactions in Electromagnetic Compatibility, Nanotechnology, Springer, Taylor and Francis and several national and international reputed Conferences.

Specialization

VLSI, Nanotechnology, Numerical Method Techniques--FDTD, Design Techniques and Modelling Schemes of High-speed on-chip VLSI Interconnects, Modeling and Simulation Schemes, Advanced Devices and Their Modeling, Analysis

Publications

  • Y. Agrawal, M. Girish, and R. Chandel, “An efficient and novel FDTD method based performance investigation in-high speed current-mode signaling SWCNT bundle interconnect”, Springer Sadhana, Indian Academy of Sciences, vol. 43, pp. 175-1-12, 2018.
  • N. Patel and Y. Agrawal, “A literature review on next generation graphene interconnects”, Journal of Circuits, Systems, and Computers, World Scientific, 2018.
  • N. Patel, Y. Agrawal, and R. Parekh, “Novel subthreshold modeling of advanced on-chip grapehne interconnect using numerical method analysis”, IETE J. Research, Taylor & Francis, 2018.
  • M. Girish, Y. Agrawal, and R. Chandel, “Modeling and performance analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects”, IET Circuits, Devices and Systems, vol. 11, no. 3, pp. 232-240, 2017.
  • Y. Agrawal, R. Chandel, and R. Dhiman, “Variability analysis of stochastic parameters on the electrical performance of on-Chip current-mode interconnect system”, IETE J. Research, Taylor & Francis, vol. 63, no. 2, pp. 268-280, 2016.
  • Y. Agrawal, M. Girish, and R. Chandel, “A Comprehensive model for high-speed current-mode signaling in next generation MWCNT bundle interconnect using FDTD technique” IEEE Trans. Nanotechnology, vol. 15, no. 4, pp. 590-598, 2016. Cite (2). DOI: https://doi.org/10.1109/TNANO.2016.2558475
  • Y. Agrawal, M. Girish, and R. Chandel, “A Novel Unified Model for Copper and MLGNR Interconnects using Voltage and Current-Mode Signaling Schemes” IEEE Trans. Electromagnetic Compatibility, vol. 59, no. 1, pp. 217-227, 2017. Cite (2). DOI: https://doi.org/10.1109/TEMC.2016.2587821
  • M. Girish, R. Chandel, and Y. Agrawal, “An efficient crosstalk model for coupled multiwalled carbon nanotube interconnects”, IEEE Trans. Electromagnetic Compatibility, vol. 60, no. 2, pp. 487-496, 2018. DOI: https://doi.org/10.1109/TEMC.2017.2719052
  • Y. Agrawal and R. Chandel, “Crosstalk analysis of current-mode signalling-coupled RLC interconnects using FDTD technique”, IETE Tech. Review, Taylor & Francis, vol. 33, no. 2, pp. 148-159, 2016. Cite (8). DOI: https://doi.org/10.1080/02564602.2015.1056258
  • Y. Agrawal, M. Girish, and R. Chandel, “A unified delay, power and crosstalk model for current mode signaling multiwall carbon nanotube interconnects”, Springer Circuits, Systems, and Signal Processing, pp. 1-31, 2017. DOI:  https://doi.org/10.1007/s00034-017-0614-6

Teaching

  • Digital Logic Design
  • Digital Design using HDL and FPGA
  • CAD of VLSI
  • Introduction to Digital Design
  • Introduction to VLSI Circuits
  • Engineering Design Workshop
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