Dhirubhai Ambani University (formerly DA-IICT), Gandhinagar, successfully organized a five-day workshop titled "RTL to GDS-II: VLSI Design and Hardware Security for Trusted Memory Systems" from July 6–10, 2026. The workshop was supported by the Anchor Institute Program (AIP).

The workshop offered participants an immersive learning experience, combining expert lectures with extensive hands-on sessions covering the complete digital VLSI design flow — spanning RTL design, memory design, hardware security, and GDS-II implementation. Participants gained practical exposure to both Cadence EDA tools and open-source EDA platforms, enabling them to develop a strong understanding of contemporary chip design methodologies and workflows.

The technical sessions were delivered by:

• Prof. Yash Agrawal, Dhirubhai Ambani University
• Prof. Sreeja Rajendran, Dhirubhai Ambani University
• Prof. Gaurav Purohit, CSIR-CEERI, Pilani

The workshop drew enthusiastic participation from faculty members, technical staff, research scholars, and students representing diverse institutions. Interactive sessions, practical exercises, and engaging discussions fostered a rich environment for learning and knowledge exchange throughout the program.

Dhirubhai Ambani University (DAU) expresses its sincere gratitude to the distinguished resource persons, participants, organizing committee, and support staff whose efforts contributed to the successful execution of the program.

As the semiconductor ecosystem continues to evolve, DAU remains committed to fostering industry-relevant skills, promoting cutting-edge research, and creating opportunities for collaborative learning through such academic initiatives.